NOTE: I AM ONLY REFERRING TO FLIP FLOPS AND NOT NECESSARILY LATCHES IN THIS PASSAGE
The D Flip Flop is a edge-triggered synchronous device that allows the user to define functionality based on clock edges to forward an input. It is a common and beginner friendly construct, and everything from Clock Trees to Fully Registered combinational circuits, it is an element that needs no better introduction.
This flip flop provided has an active low reset pin, meaning that when the pin drives a 0 logic state, or
equivalently ground, the internal logic resets the output to be some 0
state. This can be configured based
on the parameter passed to it. The reset pin is also asynchronous, meaning that the pin itself does not wait
for some timing element to be complete for it to reset.
There are more flip flops possible than just the D flip flop, JK flip flops are rather common as well. However in most of my modern academia and in other projects as well I find the D flip flop being a component that is used more commonly than other latches or flip flops.
The characteristic equation for a DFF is as follows: Q* = D
Q* := The next state of the output Q
D := The current input
module dff_simple(
// input and output ports
input logic d,
input logic clk,
output logic q
);
// sensitivity list
always_ff @(posedge clk) begin
// non-blocking operator within begin-end block
// which does not affect latency or delays
// if other outputs were all channeled using NBA
// (NBA = Non-Blocking Assignment)
//
// does not create race conditions b/c only one
// always block to compute
q <= d;
end
endmodule
